Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 36)

hardware. You can run the testbench to observe the IP core behavior on the various interfaces in
simulation.
Altera offers testbenches for the following configurations:
• All non-40GBASE-KR4 IP core variations that generate their own TX MAC clock (Use external TX
MAC PLL is turned off).
• 40GBASE-KR4 IP core variations that have Avalon-ST client interfaces and generate their own TX
MAC clock (Use external TX MAC PLL is turned off).
Currently, the IP core can generate a testbench and example project for variations that use an external TX
MAC PLL, but these testbenches and example projects do not function correctly. Non-functional
testbenches and example projects provide an example of the connections you must create in your design
to ensure the LL 40-100GbE IP core functions correctly. However, you cannot simulate them nor run
them in hardware.
To generate the testbench, in the Low Latency 40-100GbE parameter editor, you must first set the
parameter values for the IP core variation you intend to generate. If you do not set the parameter values
identically, the testbench you generate might not exercise the IP core variation you generate. If your IP
core variation does not meet the criteria for a testbench, the generation process does not create a
testbench (with the exception of the non-functional testbench generated if an IP core requires an external
TX MAC clock signal).
You can simulate the testbench that you generate with your IP core variation. The testbench illustrates
packet traffic, in addition to providing information regarding the transceiver PHY. The 40GBASE-KR4
testbench exercises auto-negotiation and link training, in addition to generating and checking packet
traffic.
Related Information
• Generating the Low Latency 40-100GbE Testbench on page 2-28
• Simulating the Low Latency 40-100GbE IP Core With the Testbenches on page 2-27
Instructions to simulate the 40GbE or 100GbE IP core with the IP core appropriate testbench you can
generate, including simulation parameters and supported simulators.
Low Latency 40-100GbE IP Core Testbench Overview
The non-40GBASE-KR4 testbenches send traffic through the IP core in transmit-to-receive loopback
mode, exercising the transmit side and receive side of the IP core in the same data flow. These testbenches
send traffic to allow the Ethernet lanes to lock, and then send packets to the transmit client data interface
and check the data as it returns through the receive client data interface.
2-22 Low Latency 40-100GbE IP Core Testbench Overview
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2015.05.04
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