Functional description, Functional description -1 – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 46
Functional Description
3
2015.05.04
UG-01172
This chapter provides a detailed description of the Low Latency 40-100GbE IP core. The chapter begins
with a high-level overview of typical Ethernet systems and then provides detailed descriptions of the
MAC, transmit (TX) and receive (RX) datapaths, signals, register descriptions, and an Ethernet glossary.
This chapter includes the following sections:
Low Latency 40-100GbE MAC and PHY Functional Description
on page 3-55
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