Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 171
Word Addr
Bit
R/W
Name
Description
0x4D0
14:12
RW
equal_cnt [2:0]
Adds hysteresis to the error count to avoid local
minimums. The following values are defined:
• 000 = 0
• 001 = 1
• 010 = 2
• 011 = 3
• 100 = 4
• 101 = 8
• 110 = 16
• 111 = reserved
The default value is 010.
15
RW
disable Initialize
PMA on max_wait_
timeout
When set to 1, PMA values (VOD, Pre-tap, Post-
tap) are not initialized upon entry into the
Training_Failure
state. This happens when
max_
wait_timer_done
, which sets
training_failure
= true (reg 0xD2 bit 3). Used for UNH testing.
When set to 0, PMA values are initialized upon
entry into
Training_Failure
state. Refer to Figure
72-5 of IEEE 802.3ap-2007 for more details.
16
RW
Ovride LP Coef
enable
When set to 1, overrides the link partner's
equalization coefficients; software changes the
update commands sent to the link partner TX
equalizer coefficients. When set to 0, uses the Link
Training logic to determine the link partner
coefficients. Used with 0x4D1 bit-4 and 0x4D4
bits[7:0].
17
RW
Ovride Local RX
Coef enable
When set to 1, overrides the local device equaliza‐
tion coefficients generation protocol. When set, the
software changes the local TX equalizer
coefficients. When set to 0, uses the update
command received from the link partner to
determine local device coefficients. Used with
0x4D1 bit-8 and 0x4D4 bits[23:16]. The default
value is 0.
B-12
10GBASE-KR PHY Register Definitions
UG-01172
2015.05.04
Altera Corporation
Arria 10 10GBASE-KR Registers