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Statistics counters interface, Statistics counters interface -34 – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 79

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Signal Name

Direction

Description

link_fault_gen_en

Output

The IP core asserts this signal if the PCS is enabled to generate a

remote fault sequence on the Ethernet link when appropriate.

Connects to the

Link Fault Reporting Enable

field in bit [0] of

the

LINK_FAULT_CONFIG

register at offset 0x405.

This signal is clocked by

clk_status

.

If you turn off Enable link fault generation this signal is not

available.

Related Information

Link Fault Signaling Registers

on page 3-70

Information about the

Link Fault Reporting Enable

register and the

Unidir Enable

register.

IEEE website

The IEEE 802.3ba –2010 100G Ethernet Standard and the IEEE 802.3 –2012 Ethernet Standard are

available on the IEEE website.

Statistics Counters Interface

The statistics counters modules are synthesis options that you select in the Low Latency 40-100GbE

parameter editor. However, the statistics status bit output vectors are provided whether you select the

statistics counters module option or not.
The increment vectors are brought to the top level as output ports.The increment vectors also function

internally as input ports to the control and status registers (CSR).

Table 3-9: Statistics Counters Increment Vectors

The TX statistics counter increment vectors are clocked by the

clk_txmac

clock, and the RX statistics counter

increment vectors are clocked by the

clk_rxmac

clock.

Name

Signal

Direction

Description

TX Statistics Counter Increment Vectors

tx_inc_64

Output

Asserted for one cycle when a 64-byte TX frame is transmitted.

tx_inc_127

Output

Asserted for one cycle when a 65–127 byte TX frame is transmitted.

tx_inc_255

Output

Asserted for one cycle when a 128–255 byte TX frame is transmitted.

tx_inc_511

Output

Asserted for one cycle when a 256–511 byte TX frame is transmitted.

tx_inc_1023

Output

Asserted for one cycle when a 512–1023 byte TX frame is transmitted.

tx_inc_1518

Output

Asserted for one cycle when a 1024–1518 byte TX frame is transmitted.

3-34

Statistics Counters Interface

UG-01172

2015.05.04

Altera Corporation

Functional Description

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