Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 150)

Addr Name Bit Description HW Reset
Value
Access
0xB05
RX_PTP_CLK_
PERIOD
[19:0]
clk_rxmac
clock period.
Bits [19:16]: nanoseconds
Bits [15:0]: fraction of nanosecond
This value is
set to the
correct clock
period for the
required RX
MAC clock
frequency.
The clock
period is
different for
40GbE
variations and
100GbE
variations.
RW
Related Information
• 1588 Precision Time Protocol Interfaces on page 3-38
• PTP Transmit Functionality on page 3-43
Ethernet Glossary
Table 3-32: Ethernet Glossary
Provides definitions for some terms associated with the Ethernet protocol.
Term Definition
BIP Bit Interleaved Parity. A diagonal parity field which is carried in the periodic
alignment markers on each virtual lane, allowing isolation of a bit error to a
physical channel.
CAUI 100 gigabit attachment unit interface. (C is the symbol in Roman Numerals for
100). This is an electrical interface that which is based on a 10-lane interface with
a bandwidth of 10 Gbps per lane. (In this implementation, the PMA multiplexes
the 20 PCS lanes into 10 physical lanes.
CGMII 100 gigabit media independent interface. (C is the symbol in Roman Numerals
for 100). This is the byte-oriented interface protocol that connects the PCS and
MAC.
DIC Deficit Idle Counter. A rule for inserting and deleting idles as necessary to
maintain the average IPG. The alternative is to always insert idles which could
lead to reduced bandwidth.
FCS Frame Check Sequence. A CRC-32 with bit reordering and inversion.
UG-01172
2015.05.04
Ethernet Glossary 3-105
Functional Description Altera Corporation
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