Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 101)

Figure 3-28: Top-Level Signals of the Low Latency 40-100GbE IP Cores
In the figure, = 4 for the 40GbE IP cores and = 8 for the 100GbE IP cores. is log
2
(8*). In
the custom streaming client interface, = 2 for the 40GbE IP core and = 4 for the 100GbE IP
core. is the number of transceiver PHY links (4 for 40GbE and CAUI-4 IP cores, and 10 for standard
100GbE IP cores). is the number of priority flow control queues. ( = 1 for IP cores configured
with standard flow control or with no flow control, and = the value of the relevant parameter for IP
cores configured with priority-based flow control).
Low Latency 40-100GbE IP Core
rx_serial [-1:0]
tx_serial [-1:0]
Asynchronous
Reset Signal
Avalon-MM
Control
and Status
Interface
Pause Control
and Generation
1588 Precise Timing
Protocol Interface
Link Fault Signaling
reset_async
status_addr [15:0]
reset_status
status_read
status_write
status_writedata [31:0]
status_readdata [31:0]
status_readdata_valid
status_waitrequest
status_read_timeout
Avalon-MM
Arria10
Transceiver
Reconfiguration
Interface
reconfig_address[13:0]
reconfig_reset
reconfig_from_xcvr
reconfig_to xcvr
reconfig_read
reconfig_write
reconfig_writedata [31:0]
reconfig_readdata [31:0]
reconfig_waitrequest
pause_receive_rx[-1:0]
pause_insert_tx[-1:0]
remote_fault_status
local_fault_status
Transceiver Serial
Data lanes
@ 10.3125 Gbps or
25.78125 Gbps
Increment Vectors of
Statistics Counters
rx_statistic_counters[26:0]
tx_statistic_counters[21:0]
ptp_pkt_out
tx_in_ptp_offset[15:0]
tx_in_ptp_overwrite[1:0]
tx_in_ptp
tod_tx_clk_st2[95:0]
rx_tod[95:0]
RX PHY Status
rx_pcs_ready
TX Avalon-ST
Client Interface
RX Avalon-ST
Client Interface
l_tx_data[(64 x )-1:0]
l_tx_empty[-1:0]
l_tx_startofpacket
l_tx_endofpacket
l_tx_ready
l_tx_valid
l_rx_data[(64 x )-1:0]
l_rx_empty[-1:0]
l_rx_startofpacket
l_rx_endofpacket
l_rx_error[5:0]
l_rx_valid
l_rx_fcs_valid
l_rx_fcs_error
l_rx_status[2:0]
l_tx_error
TX Custom
Client Interface
RX Custom
Client Interface
din[(64 x )-1:0]
din_sop[-1:0]
din_eop[-1:0]
din_eop_empty[11:0]
din_idle[-1:0]
tx_error[-1:0]
din_req
dout_d[(64 x )-1:0]
dout_c[(8 x )-1:0]
dout_sop[-1:0]
dout_eop[-1:0]
dout_eop_empty[-1:0]
dout_idle[-1:0]
rx_fcs_error
rx_fcs_valid
rx_status[2:0]
dout_valid
Clocks
clk_txmac_in
clk_rxmac
clk_rx_recover
clk_status
reconfig_clk
clk_ref
External PLL Interface
for Arria 10 Devices
Interface to Stratix V
Transceiver Reconfiguration
Controller
tx_serial_clk [-1:0]
pll_locked
rx_inc_octetsOK[15:0]
tx_inc_octetsOK[15:0]
rx_inc_octetsOK_valid
tx_inc_octetsOK_valid
OctetOK Count Interface
unidirectional_en
link_fault_gen_en
tod_txmac_in
tod_rxmac_in
tx_in_zero_tcp
tx_in_tcp_offset[15:0]
clk_txmac
rx_error[5:0]
tx_lanes_stable
3-56 Low Latency 40-100GbE IP Core Signals
UG-01172
2015.05.04
Altera Corporation Functional Description
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