Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 176
Word Addr
Bit
R/W
Name
Description
0x4D4
13:8
RO
LD coefficient
status[5:0]
Status report register for the contents of the
second, 16-bit word of the training frame most
recently sent from the local device control channel.
The following fields are defined:
• [5:4]: Coefficient (post-tap)
• 2'b11: Maximum
• 2'b01: Minimum
• 2'b10: Updated
• 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• [1:0]: Coefficient (pre-tap) (same encoding as
[5:4])
For more information, refer to 10G BASE-KR LD
status report register bit (1.155.5:0) in Clause
45.2.1.81 of IEEE 802.3ap-2007.
14
RO
Link Training ready
- LD Receiver ready
When set to 1, the local device receiver has
determined that training is complete and is
prepared to receive data. When set to 0, the local
device receiver is requesting that training continue.
Values for the receiver ready bit are defined in
Clause 72.6.10.2.4.4. For more information, refer to
10G BASE-KR LD status report register bit
(1.155.15) in Clause 45.2.1.81 of IEEE 802.3ap-
2007.
UG-01172
2015.05.04
10GBASE-KR PHY Register Definitions
B-17
Arria 10 10GBASE-KR Registers
Altera Corporation