Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 37)

Figure 2-5: Low Latency 40-100GbE non-40GBASE-KR4 IP Core Testbench
Illustrates the top-level modules of the Low Latency 40GbE and 100GbE example testbenches. Dotted
lines illustrate that for IP core variations without adapters, the testbench connects directly to the TX and
RX MAC.
Low Latency 40GbE and 100GbE
MegaCore Function
Packet
Generator
Packet
Checker
Sample
ROM
Sample
ROM
Test Controller
TX MAC
RX MAC RX PHY
TX PHY
Adapter
Adapter
Memory Map Register
Read/Write Handler
Figure 2-6: 40GBASE-KR4 LL 40GbE IP Core Testbench
Illustrates the top-level modules of the LL 40GBASE-KR4 example testbench. To support the simulation
of auto-negotiation, the testbench uses two instances of the IP core instead of configuring the IP core in
loopback mode.
Random
Skew
Test Controller
& Test Result Checker
Packet
Generator
Packet
Sanity Check
Altera Transceiver Reconfiguration Controller
IP Core
Altera Transceiver Reconfiguration Controller
IP Core
Packet
Generator
Packet
Sanity Check
Transmit Adapter
Receive Adapter
40GBASE-KR4 LL 40GbE
IP Core
without Adapter
Avalon-MM
Register Poll
Write Control
Transmit Adapter
Receive Adapter
40GBASE-KR4 LL 40GbE
IP Core
without Adapter
40GBASE-KR4 LL 40GbE MegaCore Function
with Adapter
40GBASE-KR4 LL 40GbE MegaCore Function
with Adapter
4 4
TX Txvr
PLL
TX Txvr
PLL
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core Testbench Overview 2-23
Getting Started Altera Corporation
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