Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 159
To set up, compile, and configure the project, follow these steps:
1. Close the project in which you generated the example project. You cannot run the LL 40-100GbE
example project from within your own project.
2. In the Quartus II software, on the File menu, click Open Project.
3. Navigate to the example project folder, select the Quartus Project File (.qpf),
eth_ex_{40g,100g}_
{sv,a10,kr4_a10}.qpf
(or
eth_{40g,100g}_{s5,a10}.qpf
), and click Open.
4. On the Processing menu, click Start Compilation. The Quartus II software provides static timing and
resource utilization reports.
In the case of the
eth_ex_{40g,100g}_{sv,a10,kr4_a10}.qpf
projects, the Quartus II software also generates
a SRAM Object File (
.sof
) with which you can configure your Altera device.
5. Configure your device with the generated
.sof
file.
This option is available for the newer example projects in the
eth_ex_{40g,100g}_{sv,a10,kr4_a10}.qpf
files.
The generated example project includes the following files:
• Quartus II Project File (.qpf)—Contains the Quartus II build project.
• Quartus II Settings File (.qsf)—Contains the Quartus II settings and constraints applied to this project
in synthesis: constraints on the specific Arria 10 target device, location of the IP core HDL files,
location of the .sdc file, LogicLock
™
region information, partition information, pin constraints, and
compilation directions to the Fitter.
• Synopsys Design Constraints (.sdc) file—Contains the static timing constraints applied to this project
in synthesis.
• Top level Verilog file (.v)—Contains an instance of your IP core and for Arria 10 variations, one or two
ATX PLLs. The number of TX PLLs and the clock network configuration is one choice among many
options for workable configurations. In your own design you can use this configuration or build your
own.
A-6
Compiling the Low Latency 40-100GbE IP Core Example Project
UG-01172
2015.05.04
Altera Corporation
Low Latency 40-100GbE IP Core Example Project