Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
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• Optional custom streaming data path interface with narrower bus width and a start frame possible on
64-bit word boundaries without the optional adapters. Interface has data width 128 or 256 bits
depending on the data rate.
• Support for jumbo packets.
• TX and RX CRC pass-through control.
• Optional TX CRC generation and insertion.
• RX CRC checking and error reporting.
• TX error insertion capability supports test and debug.
• RX and TX preamble pass-through options for applications that require proprietary user management
information transfer.
• TX automatic frame padding to meet the 64-byte minimum Ethernet frame length at the LL
40-100GbE Ethernet connection.
• Hardware and software reset control.
• Pause frame filtering control.
• Received control frame type indication.
• MAC provides cut-through frame processing.
• Optional deficit idle counter (DIC) options to maintain a finely controlled 8-byte or 12-byte inter-
packet gap (IPG) minimum average.
• Optional IEEE 802.3 Clause 31 Ethernet flow control operation using the pause registers or pause
interface.
• Optional priority-based flow control that complies with the IEEE Standard 802.1Qbb-2011—
Amendment 17: Priority-based Flow Control, using the pause registers for fine control.
• RX PCS lane skew tolerance that exceeds the IEEE 802.3-2012 Ethernet standard clause 82.2.12
requirements: 1900 bits RX lane skew tolerance for LL 40GbE IP cores and 1000 bits RX lane skew
tolerance for LL 100GbE IP cores.
• Optional support for the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol (1588
PTP).
• Optional statistics counters.
• Optional fault signaling: detects and reports local fault and generates remote fault, with IEEE
802.3ba-2012 Ethernet Standard Clause 66 support.
• Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
The LL 40-100GbE IP core can support full wire line speed with a 64-byte frame length and back-to-back
or mixed length traffic with no dropped packets.
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3ba-2010 High Speed Ethernet
Standard.
Related Information
The IEEE 802.3ba-2010 High Speed Ethernet Standard and the IEEE Standard 802.1Qbb-2011—
Amendment 17: Priority-based Flow Control are available on the IEEE website.
UG-01172
2015.05.04
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
1-3
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Altera Corporation