Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 189
Date
Compatible ACDS
Version
Changes
• Removed text of optimization parameter display
initial
block
Optimizing the Low Latency 40-100GbE IP Core Simulation
on page 2-29. Refer to the testbench for your
IP core variation for the correct HDL code for the variation.
• Changed default value of 40GBASE-KR4 link training PMA
parameter
INITPOSTVAL
from 22 to 13, in
page 2-5.
• Updated descriptions of IP core example project. The IP core now
generates an example project that is configurable on a device, for
most variations. The older type of example projects, which are not
configurable, are also generated. Refer to
on page 5-1.
• Fixed assorted minor errors and typos.
2014.12.17
14.1
• Corrected PTP usage figures in Implementing a 1588 System That
Includes a LL 40-100GbE IP Core.
• Clarified that user-defined extra latency is included in calculation of
PTP exit timestamp in both one-step mode and two-step mode, in
PTP Transmit Functionality.
• Clarified that TOD module is expected to provide the current
continuously updating time of day. The output signals of this
module must provide the current time of day on every clock cycle,
in V2 format.
• Moved External Time-of-Day Module for 1588 PTP Variations into
the 1588 PTP section of the Functional Description chapter.
2014.12.15
14.1
• Updated release-specific information for the software release v14.1.
• Moved licensing information and the description of the OpenCore
Plus evaluation feature to Getting Started chapter.
• Added option to instantiate the TX MAC PLL outside the IP core.
The new PLL generates the TX MAC clock. Added new parameter
Use external TX MAC PLL. If you turn on this parameter the IP
core has an additional input clock signal
clk_txmac_in
.Changes
primarily located in new sections External TX MAC PLL in Getting
Started chapter and External TX MAC PLL in Functional Descrip‐
tion chapter, in IP Core Parameters section, and in Clocks section.
• Added support for new 40GBASE-KR4 LL 40GbE IP core variation.
Changes located in existing IP Core Parameters section and
descriptions of the testbench for these IP core variations in the Low
Latency 40-100GbE IP Core Testbenches section. Added new
sections Clock Requirements for 40GBASE-KR4 Variations, Low
Latency 40GBASE-KR4 IP Core Variations, and LL 40GBASE-KR4
Registers, and a reference appendix Arria 10 10GBASE-KR
Registers.
• Added new six-bit RX error signal on client interface. On Avalon-
ST client interface,
l
replaces single-bit RX
error signal
l
. On custom client interface,
rx_
error[5:0]
is new signal.
UG-01172
2015.05.04
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
D-3
Additional Information
Altera Corporation