Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 136)

Addr Name Bit Description HW Reset
Value
Access
0x60F
TX_PFC_
SADDRL
[31:0]
TX_PFC_SADDRH
contains the 16 most signifi‐
cant bits of the source address for PFC pause
frames.
TX_PFC_SADDRL
contains the 32 least signifi‐
cant bits of the source address for PFC pause
frames.
These registers are present only if you set the
value of Flow control mode to Priority-
based flow control in the LL 40-100GbE
parameter editor.
0xCBFC_
5ADD
RW
0x610
TX_PFC_
SADDRH
[15:0] 0xE100 RW
Table 3-27: RX Ethernet Flow Control (Pause Functionality) Registers
Some registers are different depending on whether you select Standard flow control or Priority-based flow
control in the Low Latency 40-100GbE parameter editor. Where the difference is only whether the register refers
to the single standard flow control priority class or whether distinct bits in the register refer to the individual
priority queues, the two uses are documented together. In that case we understand that standard flow control
effectively supports a single priority queue.
Addr Name Bit Description HW Reset
Value
Access
0x700
RXSFC_REVID
[31:0] RX standard flow control module revision
ID.
0x01282014 RO
0x701
RXSFC_
SCRATCH
[31:0] Scratch register available for testing. 32'b0 RW
0x702
RXSFC_NAME_
0
[31:0] First 4 characters of IP core variation
identifier string "40gSFCRxCSR" or
"100gSFCRxCSR".
RO
0x703
RXSFC_NAME_
1
[31:0] Next 4 characters of IP core variation
identifier string "40gSFCRxCSR" or
"100gSFCRxCSR".
RO
0x704
RXSFC_NAME_
2
[31:0] Final 4 characters of IP core variation
identifier string "40gSFCRxCSR" or
"100gSFCRxCSR".
RO
0x705 RX_PAUSE_
ENABLE
[N-
1:0]
cfg_enable
bits. When bit [n] has the value
of 1, the RX MAC processes the incoming
pause frames for priority class n whose
address matches
{DADDR1[31:0],DADDR0[15:0]}. When bit
[n] has the value of 0, the RX MAC does not
process any incoming pause frames for
priority class n.
When the RX MAC processes an incoming
pause frame with an address match, it notifies
N'b1...1 (1'b1
in each
defined bit)
RW
UG-01172
2015.05.04
Pause Registers 3-91
Functional Description Altera Corporation
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