Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 48)

The Low Latency 40-100GbE IP core includes the following interfaces:
• Datapath client-interface–The following options are available:
• 40GbE with adapters—Avalon-ST, 256 bits
• 40GbE—Custom streaming, 128 bits
• 100GbE with adapters—Avalon-ST, 512 bits
• 100GbE—Custom streaming, 256 bits
• Management interface—Avalon-MM host slave interface for MAC management. This interface has a
data width of 32 bits and an address width of 16 bits.
• Datapath Ethernet interface–The following options are available:
• 40GbE—Four 10.3125 Gbps serial links
• 100GbE—Ten 10.3125 Gbps serial links
• 100GbE CAUI–4—Four 25.78125 Gbps serial links
• In Arria 10 variations, an Arria 10 dynamic reconfiguration interface—an Avalon-MM interface to
read and write the Arria 10 Native PHY IP core registers. This interface supports dynamic reconfigura‐
tion of the transceiver. Low Latency 40-100GbE IP cores that target an Arria 10 device use the Arria 10
Native PHY IP core to configure the Ethernet link serial transceivers on the device. This interface has a
data width of 32 bits. This interface has an address width of 12 bits for 40GbE and 100GbE CAUI-4
variations, and an address width of 14 bits for standard 100GbE variations.
Low Latency 40-100GbE IP Core TX Datapath
The TX MAC module receives the client payload data with the destination and source addresses and then
adds, appends, or updates various header fields in accordance with the configuration specified. The MAC
does not modify the destination address, the source address, or the payload received from the client.
However, the TX MAC module adds a preamble (if the IP core is not configured to receive the preamble
from user logic), pads the payload of frames greater than eight bytes to satisfy the minimum Ethernet
frame payload of 46 bytes, and if you set Enable TX CRC insertion or turn on flow control, calculates the
CRC over the entire MAC frame. (If padding is added, it is also included in the CRC calculation. If you
turn off Enable TX CRC insertion, the client must provide the CRC bytes and must provide frames that
have a minimum size of 64 bytes and therefore do not require padding). If you set Average interpacket
gap to 8 or 12, the TX MAC module inserts IDLE bytes to maintain an average IPG. In addition, the TX
MAC inserts an error in the Ethernet frame if the client requests to insert an error.
The Low Latency 40-100GbE IP core does not process incoming frames of less than nine bytes correctly.
You must ensure such frames do not reach the TX client interface.
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core TX Datapath 3-3
Functional Description Altera Corporation
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