Simulating with the modelsim simulator, Simulating with the modelsim simulator -29 – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 43

•

Low Latency 40-100GbE IP Core Example Project

on page 5-1

Altera provides an example Quartus II project with the Low Latency 40-100GbE IP core. This example

project can compile and configure on an Altera device. In addition, for Arria 10 IP core variations, you

can use this example project to view one option for connecting the external TX PLL or TX PLLs in your

design.

Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches

In the testbench file for non-40GBASE-KR4 variations, you can set the

FASTSIM

parameter and force

values in the

RO_SELS

BPOS

, and

WPOS

parameters to enable simulation optimization. The testbench also

specifies another IP core simulation optimization setting that you might need to modify for simulation in

your own environment:

AM_CNT_BITS

To derive the values to which to force the

RO_SELS

BPOS

, and

WPOS

parameters, you must run your first

simulation with some additional testbench code to display the simulation-derived values. For subsequent

simulation runs with the same hardware design and simulator, you can force the values to these

simulation-derived values to avoid the lengthy simulation required to achieve lane alignment. The process

is particularly slow for this IP core because the IP core includes a soft processor that drives the lane

alignment process. Forcing the parameters to the correct values for your design and simulator bypasses

this process, increasing simulation efficiency.
The testbench file generated with the Low Latency 40-100GbE IP core includes an

initial

block that

displays the required force values. You can view the appropriate

initial

block for your IP core variation

in the top-level testbench file you generate with your example design.
When you run simulation, this initial block prints values for the three parameters after lane alignment.

Copy the values from standard output or from your log file and add the following lines to the testbench

file, overwriting other forced values for these parameters if necessary:

defparam dut.top_inst.FASTSIM = 1;
defparam dut._inst.FORCE_BPOS = ;
defparam dut._inst.FORC_WPOS = ;
defparam dut._inst.FORCE_RO_SELS = ;

Note: Whether you use the Altera-provided testbench or your own custom testbench, you must update

the testbench file with these lines and the derived values. The testbench file generated with the Low

Latency 40-100GbE IP core does not include the correct values, which depend on your IP core

variation and simulation tool.

The

AM_CNT_BITS

parameter specifies the interval between expected alignment markers. The default value

of this parameter is 14; this value specifies that alignment markers are inserted every 2

blocks, in

compliance with the Ethernet specification. However, the testbench sets this parameter to the value of 6,

to speed up simulation. In your own simulation environment, you must set this parameter to match the

interval between incoming alignment markers to the IP core.

Simulating with the Modelsim Simulator

To run the simulation in the supported versions of the ModelSim simulation tool, follow these steps:
1. Change directory to the

_example_design/alt_eth_ultra/example_testbench