Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 155)

Connections in the Low Latency 40-100GbE IP Core Example Project
You can use the example project to illustrate one correct method to connect your IP core to your design,
or as a starter design you can customize for your own design requirements.
You can compile the project and configure it on the Arria 10 FPGA Signal Integrity Development Kit or
the 100G Development Kit, Stratix V GX Edition. For CAUI-4 IP core variations and variations that have
a custom streaming client interface (without adapters), you can use the legacy example project to perform
static timing analysis.
Figure A-1: High Level Block Diagram for the Arria 10 40-100GbE Non-CAUI-4 Example Project
The example projects for standard 40GbE and 100GbE IP core variations and 40GBASE-KR4 variations
that target an Arria 10 device configure a single ATX PLL and connect it to the xN clock network, which
distributes the output
tx_serial_clk
signal to all four or ten individual transceiver channels. If this
arrangement is not available for your design, you can use multiple external ATX and CMU PLLs to
generate and distribute the
tx_serial_clk
signals for the individual channels. This example project also
includes client logic to exercise the IP core. The client logic includes logic to ensure each packet is sent to
the Avalon-ST interface without any intermediate idle cycles, in other words, that the data sent to this
interface complies with the IP core requirements.
Low latency 40- or 100-Gbps Ethernet MAC and PHY
MegaCore Function
Low Latency 40- or 100-Gbps Ethernet Example Project for non-CAUI-4 Arria 10 IP Core Variations
Altera FPGA
TX
FIFO
MAC Transceiver PHY
ATX
PLL
Avalon-ST
pll_locked
tx_serial_clk[9:0] or [3:0]
Transceiver
xN clock network
Avalon-ST
Control and
Status Interface
Avalon-MM
Arria 10 Transceiver
Reconfiguration
Interface
...
Client
Logic
PMD
Optical
Module
CFP
or
QSFP
A-2 Connections in the Low Latency 40-100GbE IP Core Example Project
UG-01172
2015.05.04
Altera Corporation Low Latency 40-100GbE IP Core Example Project
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