Debugging the 40gbe and 100gbe link, Debugging the 40gbe and 100gbe link -1 – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
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Debugging the 40GbE and 100GbE Link
4
2015.05.04
UG-01172
If you are experiencing difficulties bringing up your Low Latency 40-100GbE IP core link in hardware,
Altera suggests that you begin debugging at the most basic level, with word lock. Then, consider higher
level issues.
The following steps should help you identify and resolve common problems that occur when bringing up
a Low Latency 40-100GbE IP core link:
1. Establish word lock—The RX lanes should be able to achieve word lock even in the presence of
extreme bit error rates. If unable to achieve word lock, check the transceiver clocking and data rate
configuration. Check for cabling errors such as the reversal of the TX and RX lanes. Check the clock
frequency monitors.
To check for word lock: Clear the
PHY_FRAME_ERROR
register by writing the value of 1 to the
PHY_SCLR_FRAME_ERROR
regiseter at offset 0x324, and then read the
PHY_FRAME_ERROR
regster at offset
0x323. If the value is non-zero then the IP core has probably not yet achieved, or has lost, word lock.
2. Establish the alignment marker lock—Virtual lane alignment marker lock requires a moderate quality
transceiver connection. If the lock is completely absent, recheck the alignment marker period. If the
lock is intermittent, recheck the transceiver physical connection and analog settings.
To check for alignment marker lock: Check the value of the
rx_pcs_ready
signal or read bit [0] of the
PHY_RXPCS_STATUS
register at offset 0x326. The value of 1 on the signal or in the register bit indicates
the RX PCS is fully aligned.
3. Establish lane integrity—When operating properly, the lanes should not experience bit errors at a rate
greater than roughly one per hour per day. Bit errors within data packets are identified as FCS errors.
Bit errors in control information including IDLE frames generally cause errors in XL/CGMII
decoding. The bit interleaved parity (BIP) mechanism is a diagonal parity computation that enables
tracing a protocol error back to a physical lane.
4. Verify packet traffic—The Ethernet protocol includes automatic lane reordering so the higher levels
should follow the PCS. If the PCS is locked, but higher level traffic is corrupted, there may be a
problem with the remote transmitter virtual lane tags.
5. Tuning—You can adjust analog parameters to minimize any remaining bit error rate. IDLE traffic is
representative for analog purposes.
Related Information
•
For information about the analog parameters for Stratix V devices.
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