Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 77)

• Processing—You can enable or disable pause frame processing. If you disable pause frame processing,
the IP core does not modify its behavior in response to incoming pause frames on the Ethernet link.
You can enable or disable pause frame processing with the
cfg_enable
bit of the
RX_PAUSE_ENABLE
register. By default, RX pause frame processing is enabled.
• Filtering—If pause frame processing is enabled, the IP core automatically performs address filtering on
incoming pause control frames before processing them. You set the matching address value in these
registers:
•
RX_PAUSE_DADDRL[31:0]
at offset 0x707
•
RX_PAUSE_DADDRH[15:0]
at offset 0x708
The 48-bit address ({
RX_PAUSE_DADDRH[15:0]
,
RX_PAUSE_DADDRL[31:0]
} can be an individual MAC
address, a multicast address, or a broadcast address.
• TX MAC filtering—For standard flow control only, Altera provides an additional level of filtering to
enable or disable the TX MAC from responding to notification from the RX MAC that it received an
incoming pause frame with an address match. Even if the RX MAC processes an incoming pause
frame, you can separately set the TX MAC to ignore the RX MAC request to pause outgoing frames, by
setting bit [0] of the
TX_XOF_EN
register to the value of 0. By default this register field has the value of 1.
• Pass-through—The Low Latency 40GbE and 100GbE MAC IP cores can pass the matching pause
packets through as normal traffic or drop these pause control frames in the RX direction. You can
enable and disable pass-through with the
cfg_fwd_ctrl
bit of the
RX_PAUSE_FWD
register. By default,
pass-through is disabled. All non-matching pause frames are passed through to the RX client interface
irrespective of the
cfg_fwd_ctrl
setting.
The following rules define pause control frames filtering control:
1. If you have disabled pause frame processing, by setting the
cfg_enable
bit of the
RX_PAUSE_ENABLE
register to the value of 0, the IP core drops packets that enter the RX MAC and match the destination
address, length, and type of 0x8808 with an opcode of 0x1 (pause packets)
2. If you have enabled pause frame processing, and the destination address in the pause frame is a match,
when the RX MAC receives a pause packet it passes a pause request to the TX MAC. The RX MAC
only processes pause packets with a valid packet multicast address or a destination address matching
the destination address specified in the
RX_PAUSE_DADDR1
and
RX_PAUSE_DADDR0
registers, or in the
RX_PAFC_DADDRH
and
RX_PFC_DADDRL
registers, as appropriate for the flow control mode . If you have
turned on pause frame pass-through, the RX MAC also forwards the pause frame to the RX client
interface. If you have not turned on pause frame pass-through, the RX MAC does not forward the
matching pause frame to the RX client interface.
3. In priority-based flow control, or in standard flow control if you have enabled TX MAC filtering, when
the TX MAC receives a pause request from the RX MAC, it pauses transmission on the TX Ethernet
link.
Pause packet pass-through does not affect the pause functionality in the TX or RX MAC.
Link Fault Signaling Interface
If you turn on Enable link fault generation in the Low Latency 40-100GbE parameter editor, the Low
Latency 40-100GbE IP core provides link fault signaling as defined in the IEEE 802.3ba-2010 100G
Ethernet Standard and Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The Low Latency 40GbE and
100GbE MAC include a Reconciliation Sublayer (RS) located between the MAC and the XLGMII or
CGMII to manage local and remote faults. Link fault signaling on the Ethernet link is disabled by default
but can be enabled by bit [0] of the
LINK_FAULT_CONFIG
register. When enabled, the local RS TX logic
transmits remote fault sequences in case of a local fault and transmits IDLE control words in case of a
remote fault.
3-32 Link Fault Signaling Interface
UG-01172
2015.05.04
Altera Corporation Functional Description
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