Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 73)

The port is expected to receive the clock from the external TX MAC PLL and drives the internal clock
clk_txmac
. The required TX MAC clock frequency is 312.5 MHz for 40GbE variations, and 390.625 MHz
for 100GbE variations. User logic must drive
clk_txmac_in
from a PLL whose input is the PHY reference
clock,
clk_ref
.
Congestion and Flow Control Using Pause Frames
If you turn on flow control by setting Flow control mode to the value of Standard flow control or
Priority-based flow control in the Low Latency 40-100GbE parameter editor, the Low Latency
40-100GbE IP core provides flow control to reduce congestion at the local or remote link partner. When
either link partner experiences congestion, the respective transmit control sends pause frames. The pause
frame instructs the remote transmitter to stop sending data for the duration that the congested receiver
specified in an incoming XOFF frame. In the case of priority-based flow control, the pause frame applies
to only the indicated priority class.
When the IP core receives the XOFF pause control frame, if the following conditions all hold, the IP core
behavior depends on the flow control scheme.
• In priority-based flow control, the IP core informs the TX client of the received XOFF frame. The IP
core continues to process packets it receives on the TX client interface. The IP core tracks the pause
quanta countdown internally and informs the TX client when the pause period is ended.
Note: In the priority-based flow control sceme, the client is responsible to throttle the flow of data to
the TX client interface after the IP core informs the client of the received XOFF frame.
• In standard flow control, the IP core TX MAC does not process TX packets and in fact, prevents the
client from sending additional data to the TX client interface, for the duration of the pause quanta of
the incoming pause frame.
The IP core responds to an incoming XOFF pause control frame if the following conditions all hold:
• The relevant
cfg_enable
bit of the
RX_PAUSE_ENABLE
register has the value of 1.
• In the case of standard flow control, bit [0] of the
TX_XOF_EN
register also has the value of 1.
• Address matching is positive.
The pause quanta can be configured in the pause quanta register of the device sending XOFF frames. If
the pause frame is received in the middle of a frame transmission, the transmitter finishes sending the
current frame and then suspends transmission for a period specified by the pause quanta. Data transmis‐
sion resumes when a pause frame with quanta of zero is received or when the timer has expired. The
pause quanta received overrides any counter currently stored. When more than one pause quanta is sent,
the value of the pause is set to the last quanta received.
XOFF pause frames stop the remote transmitter. XON pause frames let the remote transmitter resume
data transmission.
One pause quanta fraction is equivalent to 512 bit times. The duration of a pause quantum depends on the
client interface datapath width (256 bits for Low Latency 40GbE IP cores and 512 bits for Low Latency
100GbE IP cores) and on the system clock (
clk_txmac
) frequency (312.5 MHz for Low Latency 40GbE IP
cores and 390.625 MHz for Low Latency 100GbE IP cores).
3-28 Congestion and Flow Control Using Pause Frames
UG-01172
2015.05.04
Altera Corporation Functional Description
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