Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 112)

• Pause Registers on page 3-85
• TX Statistics Registers on page 3-92
• RX Statistics Registers on page 3-98
• 1588 PTP Registers on page 3-103
• Arria 10 Transceiver PHY User Guide
The 40GBASE-KR4 variations of the LL 40-100GbE IP core use the Arria 10 10GBASE-KR PHY IP
core PHY registers at internal offsets 0x4B0–0x4FF (at IP core register map offsets 0xB0–0xFF) and
Arria 10 FEC error insertion device registers. Information about this 10GBASE-KR PHY IP core,
including register descriptions, is available in the 10GBASE-KR PHY IP Core section in the Arria 10
Transceiver PHY User Guide.. The register descriptions are also duplicated in Arria 10 10GBASE-KR
Registers .
Low Latency 40-100GbE IP Core Registers
The following sections describe the registers included in the Low Latency 40-100GbE IP core.
PHY Registers on page 3-67
Link Fault Signaling Registers on page 3-70
LL 40GBASE-KR4 Registers on page 3-71
Low Latency 40-100GbE IP Core MAC Configuration Registers on page 3-83
Pause Registers on page 3-85
TX Statistics Registers on page 3-92
RX Statistics Registers on page 3-98
1588 PTP Registers on page 3-103
Related Information
Control and Status Interface on page 3-49
PHY Registers
Table 3-20: PHY Registers
Addr Name Bit Description HW Reset
Value
Access
0x300
PHY_REVID
[31:0] IP core PHY module revision ID. 0x02062015 RO
0x301
PHY_SCRATCH
[31:0] Scratch register available for testing. 32'b0 RW
0x302
PHY_NAME_0
[31:0] First 4 characters of IP core variation
identifier string " 40GE pcs " or "100GE pcs ".
RO
0x303
PHY_NAME_1
[31:0] Next 4 characters of IP core variation
identifier string " 40GE pcs " or "100GE pcs ".
RO
0x304
PHY_NAME_2
[31:0] Final 4 characters of IP core variation
identifier string " 40GE pcs " or "100GE pcs ".
RO
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core Registers 3-67
Functional Description Altera Corporation
Send Feedback