Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 67)

Name Direction Description
l_rx_fcs_error Output When asserted, indicates an FCS error condition. The IP
core asserts the
l_rx_fcs_error
signal only when it
asserts the
l_rx_fcs valid
signal.
Runt frames always force an FCS error condition.
However, if a packet is eight bytes or smaller, it is
considered a decoding error and not a runt frame, and the
IP core does not flag it as a runt.
l_rx_status[2:0]
Output Indicates the IP core received a control frame on the
Ethernet link. This signal identifies the type of control
frame the IP core is passing through to the client interface.
This signal is valid in EOP cycles only. To ensure you can
identify the corresponding packet, you must turn on
Enable alignment EOP on FCS word in the LL 40-
100GbE parameter editor.
The individual bits report different types of received
control frames:
• Bit [0]: Indicates the IP core received a standard flow
control frame. If the IP core is in standard flow control
mode and the
cfg_fwd_ctrl
bit of the
RX_PAUSE_FWD
register has the value of 0, this bit maintains the value
of 0.
• Bit [1]: Indicates the IP core received a priority flow
control frame. If the IP core is in priority flow control
mode and the
cfg_fwd_ctrl
bit of the
RX_PAUSE_FWD
register has the value of 0, this bit maintains the value
of 0.
• Bit [2]: Indicates the IP core received a control frame
that is not a flow control frame.
3-22 Low Latency 40-100GbE IP Core RX Data Bus
UG-01172
2015.05.04
Altera Corporation Functional Description
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