Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 114
Addr
Name
Bit
Description
HW Reset
Value
Access
0x315
PHY_PCS_
INDIRECT_
DATA
[3:0]
or
[9:0]
PCS indirect data. To read a FIFO flag, set the
value in the
PHY_PCS_INDIRECT_ADDR
register to indicate the flag you want to read.
After you set the specific flag indication in
the
PHY_PCS_INDIRECT_ADDR
register, each
bit [n] in the
PHY_PCS_INDIRECT_DATA
register has the value of that FIFO flag for the
transceiver channel for lane [n].
This register has four valid bits [3:0] in LL
40GbE IP core variations, and ten valid bits
[9:0] in standard LL 100GbE IP core
variations. This register is not valid for
CAUI-4 variations.
TX full flags
RO
0x320
PHY_TX_PLL_
LOCKED
[9:0] Each bit that is asserted indicates that the
corresponding lane TX PLL is locked.
10'b0
RO
0x321
PHY_
EIOFREQ_
LOCKED
[9:0] Each bit that is asserted indicates that the
corresponding lane RX CDR PLL is locked.
10'b0
RO
RO
0x322
PHY_TX_
COREPLL_
LOCKED
[2]
RX PLL is locked.
3'b0
RO
[1]
TX PLL is locked.
[0]
TX PCS is ready.
0x323
PHY_FRAME_
ERROR
[3:0]
or
[19:0]
Each bit that is asserted indicates that the
corresponding virtual lane has a frame error.
These bits are sticky. You clear them with the
PHY_SCLR_FRAME_ERROR
register.
0xF or
0xFFFFF
RO
0x324
PHY_SCLR_
FRAME_ERROR
[0]
Synchronous clear for
PHY_FRAME_ERROR
register. Write the value of 1 to this register
to clear the
PHY_FRAME_ERROR
register.
1'b0
RW
0x325
PHY_EIO_
SFTRESET
[1]
Set this bit to clear the RX FIFO.
2'b00
RW
[0]
RX PCS reset: set this bit to reset the RX
PCS.
0x326
PHY_RXPCS_
STATUS
[1:0] Indicates the RX PCS is fully aligned and
ready to accept traffic.
• Bit [1]: HI BER status (bit error rate is
high according to Ethernet standard
definition)
• Bit [0]: RX PCS fully aligned status
0
RO
UG-01172
2015.05.04
PHY Registers
3-69
Functional Description
Altera Corporation