Simulation environment, Compilation checking, Hardware testing – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 10: Performance and resource utilization, Simulation environment -6, Compilation checking -6, Hardware testing -6, Performance and resource utilization -6
Simulation Environment
Altera performs the following tests on the Low Latency 40-100GbE MAC and PHY IP core in the
simulation environment using internal and third party standard bus functional models (BFM):
• Constrained random tests that cover randomized frame size and contents
• Randomized error injection tests that inject Frame Check Sequence (FCS) field errors, runt packets,
and corrupt control characters, and then check for the proper response from the IP core
• Assertion based tests to confirm proper behavior of the IP core with respect to the specification
• Extensive coverage of our runtime configuration space and proper behavior in all possible modes of
operation
Compilation Checking
Altera performs compilation testing on an extensive set of Low Latency 40-100GbE MAC and PHY IP
core variations and designs that target different devices, to ensure the Quartus II software places and
routes the IP core ports correctly.
Hardware Testing
Altera performs hardware testing of the key functions of the Low Latency 40-100GbE MAC and PHY IP
core using standard 40-100Gbps Ethernet network test equipment and optical modules. The Altera
hardware tests of the Low Latency 40-100GbE IP core also ensure reliable solution coverage for hardware
related areas such as performance, link synchronization, and reset recovery. The IP core is tested with
Stratix V devices.
Performance and Resource Utilization
The following sections provide performance and resource utilization data for the Low Latency 40GbE and
100GbE IP cores.
Table 1-4: IP Core Variation Encoding for Resource Utilization Tables
"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
IP Core
Variation
A
B
C
D
E
F
Parameter
Data
interface
Custom-ST
Avalon-ST
Avalon-ST
Avalon-ST
Avalon-ST
Avalon-ST
Flow
control
mode
No flow
control
No flow
control
Standard
flow control
Standard
flow control
No flow
control
No flow control
Average
interpack
et gap
12
12
12
12
12
12
1-6
Simulation Environment
UG-01172
2015.05.04
Altera Corporation
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function