Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 53)

Table 3-2: Signals of the TX Client Interface
In the table, = 4 for the 40GbE IP core and = 8 for the 100GbE IP core. is log
2
(8*). All interface
signals are clocked by the
clk_txmac
clock.
Signal Name Direction Description
l_tx_data[*64-1:0] Input TX data. If the preamble pass-through feature is enabled,
data begins with the preamble.
The Low Latency 40-100GbE IP core does not process
incoming frames of less than nine bytes correctly. You
must ensure such frames do not reach the TX client
interface.
You must send each TX data packet without intermediate
idle cycles. Therefore, you must ensure your application
can provide the data for a single packet in consecutive
clock cycles. If data might not be available otherwise, you
must buffer the data in your design and wait to assert
l
_tx_startofpacket
when you are assured the packet data
to send on
l_tx_data[*64-1:0]
is available or
will be available on time.
l_tx_empty[-1:0] Input Indicates the number of empty bytes on
l_tx_data
when
l_tx_endofpacket
is asserted.
l_tx_startofpacket Input When asserted, indicates the start of a packet. The packet
starts on the MSB.
l_tx_endofpacket Input When asserted, indicates the end of packet.
l_tx_ready Output When asserted, the MAC is ready to receive data. The
l_tx_ready
signal acts as an acknowledge. The source
drives
l_tx_valid
and
l_tx_data[*64-1:0]
,
then waits for the sink to assert
l_tx_ready
. The
readyLatency
is zero cycles, so that the IP core accepts
valid data in the same cycle in which it asserts
l_tx_
ready
.
The
l_tx_ready
signal indicates the MAC is ready to
receive data in normal operational model. However, the
l_tx_ready
signal might not be an adequate
indication following reset. To avoid sending packets
before the Ethernet link is able to transmit them reliably,
you should ensure that the application does not send
packets on the TX client interface until after the
tx_
lanes_stable
signal is asserted.
l_tx_valid Input When asserted
l_tx_data
is valid. This signal must be
continuously asserted between the assertions of
l_tx_
startofpacket
and
l_tx_endofpacket
for the same
packet.
3-8 Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
UG-01172
2015.05.04
Altera Corporation Functional Description
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