Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 85)

Figure 3-20: Example Ethernet System with Ordinary Clock Master and Ordinary Clock Slave
You can implement both master and slave clocks using the Altera LL 40-100GbE IP core with 1588 PTP
functionality.
Packet
Parser
Packet
Parser
MAC TX
1588
MAC RX
1588
PHY
User Logic
User Logic CPU
Altera LL 40-100GbE IP Core
Packet Packet
Packet Packet Packet
rx_tod
Packet
FPGA-OC Master
T1
T4
Packet
Parser
Packet
Parser
MAC TX
1588
MAC RX
1588
PHY
User Logic
User Logic CPU
Packet Packet
Packet Packet Packet
rx_tod
Packet
FPGA-OC Slave
T3
T2
Cable
ToD
ToD ToD
Altera LL 40-100GbE IP Core
Figure 3-21: Hardware Configuration Example Using Altera LL 40-100GbE IP core in a 1588 System in
Transparent Clock Mode
Packet
Parser
Packet
Parser
MAC TX
1588
MAC RX
1588
PHY
User Logic
User Logic
Packet + Ti2
Packet + Ti1 Packet
rx_tod
Packet
FPGA-TC
Te2
Ti1
Ti2
Packet
Parser
Packet
Parser
MAC TX
1588
MAC RX
1588
PHY
ToD
User Logic
User Logic
Altera LL 40-100GbE IP Core
Packet + Ti1
Packet + Ti2 Packet
rx_tod
Packet
Te1
Ti2
Ti1
Cable Cable
ToD
Altera LL 40-100GbE IP Core
3-40 Implementing a 1588 System That Includes a LL 40-100GbE IP Core
UG-01172
2015.05.04
Altera Corporation Functional Description
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