Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 33)

You must also connect the
mgmt_clk_clk
and
mgmt_rst_reset
ports of the Altera Transceiver Reconfi‐
guration Controller. The
mgmt_clk_clk
port must have a clock setting in the range of 100–125MHz; this
setting can be shared with the Low Latency 40-100GbE IP core
clk_status
port. The
mgmt_rst_reset
port must be deasserted before, or deasserted simultaneously with, the Low Latency 40-100GbE IP core
reset_async
port.
Refer to the example project for RTL that connects the Altera transceiver reconfiguration controller to the
IP core..
Table 2-6: External Altera Transceiver Reconfiguration Controller Ports for Connection to Low Latency
40-100GbE IP Core
Signal Name Direction Description
reconfig_to_
xcvr[559:0]
(40GbE)
reconfig_to_
xcvr[1399:0]
(100GbE)
Input The Low Latency 40-100GbE IP core reconfiguration
controller to transceiver port in Stratix V devices.
reconfig_from_
xcvr[367:0]
(40GbE)
reconfig_from_
xcvr[919:0]
(100GbE)
Output The Low Latency 40-100GbE IP core reconfiguration
controller from transceiver port in Stratix V devices.
reconfig_busy Input
Indicates the reconfiguration controller is still in the
process of reconfiguring the transceiver.
Related Information
Altera Transceiver PHY IP Core User Guide
For more information about the Altera Transceiver Reconfiguration Controller.
External Transceiver PLL Required in Arria 10 Designs
Low Latency 40-100GbE IP cores that target Arria 10 devices require an external TX transceiver PLL to
compile and to function correctly in hardware.
You can use the IP Catalog to create an external transceiver PLL.
• Select Arria 10 Transceiver ATX PLL or Arria 10 Transceiver CMU PLL.
• In the parameter editor, set the following parameter values:
• PLL output frequency to 5156.25 MHz for standard LL 40-100GbE IP core variations or to
12890.625 MHz for CAUI-4 variations. The transceiver performs dual edge clocking, using both
the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency
setting supports a 10.3125 or 25.78125 Gbps data rate through the transceiver.
• PLL reference clock frequency to the value you specified for the PHY reference frequency
parameter.
When you generate a Low Latency 40-100GbE IP core, the software also generates the HDL code for an
ATX PLL, in the file /arria10_atx_pll.v . However, the HDL code for the Low Latency
40-100GbE IP core does not instantiate the ATX PLL. If you choose to use the ATX PLL provided with
the Low Latency 40-100GbE IP core, you must instantiate and connect the instances of the ATX PLL with
the LL 40-100GbE IP core in user logic.
UG-01172
2015.05.04
External Transceiver PLL Required in Arria 10 Designs 2-19
Getting Started Altera Corporation
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