Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 38
Table 2-8: Low Latency 40-100GbE IP Core Testbench File Descriptions
Lists the key files that implement the example testbenches.
File Names
Description
Testbench and Simulation Files
basic_avl_tb_top.v
Top-level testbench file for non-40GBASE-KR4
variations. The testbench instantiates the DUT and
runs Verilog HDL tasks to generate and accept
packets.
alt_e40_avalon_kr4_tb.sv
Top-level testbench file for 40GBASE-KR4
variations.
alt_e40_avalon_tb_packet_gen.v
,
alt_e40_avalon_tb_
packet_gen_sanity_check.v
,
alt_e40_stat_cntr_1port.v
Packet generator and checkers for 40GBASE-KR4
variations.
Testbench Scripts
run_vsim.do
The ModelSim script to run the testbench.
run_vcs.sh
The Synopsys VCS script to run the testbench.
run_ncsim.sh
The Cadence NCSim script to run the testbench.
2-24
Low Latency 40-100GbE IP Core Testbench Overview
UG-01172
2015.05.04
Altera Corporation
Getting Started