Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 20)

Parameter Type Range Default Setting Parameter Description
Enable SyncE Boolean • True
• False
False Exposes the RX recovered clock as
an output signal. This feature
supports the Synchronous Ethernet
standard described in the ITU-T G.
8261, G.8262, and G.8264
recommendations.
This parameter is available only in
variations that target an Arria 10
device.
PHY reference
frequency
Integer
(encodi
ng)
• 322.265625
MHz
• 644.53125 MHz
644.53125 MHz Sets the expected incoming PHY
clk_ref
reference frequency. The
input clock frequency must match
the frequency you specify for this
parameter (± 100ppm).
Use external
TX MAC PLL
Boolean • True
• False
False If you turn this option on, the IP
core is configured to expect an input
clock to drive the TX MAC. The
input clock signal is
clk_txmac_in
.
Flow Control Options
Flow control
mode
String • No flow control
• Standard flow
control
• Priority-based
flow control
No flow control Configures the flow control
mechanism the IP core implements.
Standard flow control is Ethernet
standard flow control.
If you select the custom streaming
client interface, the IP core must be
configured with no flow control,
and this parameter is not available.
Number of
PFC queues
Integer 1–8
8
Number of distinct priority queues
for priority-based flow control. This
parameter is available only if you set
Flow control mode to Priority-
based flow control.
2-6 IP Core Parameters
UG-01172
2015.05.04
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