Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 118)

Address Name Bit Description HW
Reset
Value
Access
0x0B1
SEQ Reconfig
Mode[5:0]
[13:8] Specifies the Sequencer mode for PCS
reconfiguration. The following modes are
defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 40G data mode
• Bit 11, mode[3]: GigE data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit13, mode[5]: 40G FEC mode
FEC Block
Lock
[23:20
]
FEC Block Lock for lanes [3:0]: bit [20] is FEC
block lock for lane 0, bit [21] is FEC block lock
for lane 1, bit [22] is FEC block lock for lane 2,
and bit [23] is FEC block lock for lane 3.
4'b0 RO
0xB2
KR FEC TX
Error Insert,
Lane 0
11 Writing a 1 inserts one error pulse into the TX
FEC for lane 0, depending on the Transcoder
and Burst error settings for lane 0.
You must select these settings through the Arria
10 dynamic reconfiguration interface to the
Arria 10 device registers before you write a 1 to
the KR FEC TX Error Insert, Lane 0 bit. To select
these settings for Lane 0, perform a read-modify-
write operation sequence at register offset 0xBD.
You select a Transcoder error by setting the
transcode_err
bit, resetting the
burst_err
bit,
resetting the
burst_err_len
field, and leaving
the remaining bits at their previous values.
You select a Burst error by setting the
burst_err
bit, specifying the burst error length in the
burst_err_len
field, resetting the
transcode_
err
bit, and leaving the remaining bits at their
previous values.
1'b0 RWSC
UG-01172
2015.05.04
LL 40GBASE-KR4 Registers 3-73
Functional Description Altera Corporation
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