Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 116)

Table 3-22: Link Fault Status Register—Offset 0x508
Name Bit Description HW
Reset
Value
Access
Remote Fault
Status
[1] The remote fault status register. 1'b0 RO
Local Fault
Status
[0] The local fault status register. 1'b0 RO
Related Information
Link Fault Signaling Interface on page 3-32
Describes how the IP core uses the register values.
LL 40GBASE-KR4 Registers
Most LL 40GBASE-KR4 registers are 10GBASE-KR PHY registers of the Arria 10 10GBASE-KR PHY IP
core, documented in the Arria 10 Transceiver PHY User Guide . Exceptions are:
• The register offsets of the 10GBASE-KR PHY registers are offset by negative 0x400 in the LL
40GBASE-KR4 variations of the LL 40-100GbE IP core. The Arria 10 10GBASE-KR PHY IP core
registers begin at offset 0x4B0. In the LL 40GBASE-KR4 IP core, these registers begin at offset 0x0B0.
• The LL 40GBASE-KR4 variations of the LL 40-100GbE IP core have additional 40GBASE-KR4 related
registers and register fields.
• The FEC error insertion feature requires that you program some Arria 10 device registers tthrough the
Arria 10 dynamic reconfiguration interface. The FEC error count is collected in other Arria 10 device
registers that you access through the Arria 10 dynamic reconfiguration interface. You access the
relevant Arria 10 device registers at offsets 0xBD through 0xE3 for Lane 0, 0x4BD through 0x4E3 for
Lane 1, 0x8BD through 0x8E3 for Lane 2, and 0xCBD through 0xCE3 for Lane 3. The descriptions of
the LL 40GBASE-KR4 registers that depend on these Arria 10 device registers provide the individual
A10 register information.
For your convenience, the LL 40-100GbE IP core user guide includes an appendix with the 10GBASE-KR
PHY register descriptions: Arria 10 10GBASE-KR Registers .
UG-01172
2015.05.04
LL 40GBASE-KR4 Registers 3-71
Functional Description Altera Corporation
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