Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 177)

Word Addr Bit R/W Name Description
0x4D4
21:16 RO
or
RW
LP coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the
training frame most recently received from the
control channel.
Normally the bits in this register are read only;
however, when training is disabled by setting low
the KR Training enable control bit, these bits
become writeable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
• 2'b11: Reserved
• 2'b01: Increment
• 2'b10: Decrement
• 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as
[5:4])
• [1:0]: Coefficient (-1) update (same encoding as
[5:4])
For more information, refer to 10G BASE-KR LP
coefficient update register bits (1.152.5:0) in Clause
45.2.1.78.3 of IEEE 802.3ap-2007.
22 RO
or
RW
LP Initialize
Coefficients
When set to 1, the local device transmit equalizer
coefficients are set to the INITIALIZE state. When
set to 0, normal operation continues. The function
and values of the initialize bit are defined in Clause
72.6.10.2.3.2. For more information, refer to 10G
BASE-KR LP coefficient update register bits
(1.152.12) in Clause 45.2.1.78.3 of IEEE 802.3ap-
2007.
23 RO
or
RW
LP Preset
Coefficients
When set to 1, The local device TX coefficients are
set to a state where equalization is turned off.
Preset coefficients are used. When set to 0, the local
device operates normally. The function and values
of the preset bit is defined in 72.6.10.2.3.1. The
function and values of the initialize bit are defined
in Clause 72.6.10.2.3.2. For more information, refer
to 10G BASE-KR LP coefficient update register bits
(1.152.13) in Clause 45.2.1.78.3 of IEEE 802.3ap-
2007.
B-18 10GBASE-KR PHY Register Definitions
UG-01172
2015.05.04
Altera Corporation Arria 10 10GBASE-KR Registers
Send Feedback