Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 22)

Parameter Type Range Default Setting Parameter Description
Enable TX
CRC insertion
Boolean • True
• False
True If turned on, the IP core inserts a
32-bit Frame Check Sequence (FCS)
, which is a CRC-32 checksum, in
outgoing Ethernet frames. If turned
off, the IP core does not insert the
CRC-32 sequence in outgoing
Ethernet communication. Turning
on TX CRC insertion improves
reliability but increases resource
utilization and latency through the
IP core.
If you turn on flow control, the IP
core must be configured with TX
CRC insertion, and this parameter is
not available.
Enable
preamble
passthrough
Boolean • True
• False
False If turned on, the IP core is in RX
and TX preamble pass-through
mode. In RX preamble pass-through
mode, the IP core passes the
preamble and SFD to the client
instead of stripping them out of the
Ethernet packet. In TX preamble
pass-through mode, the client
specifies the preamble to be sent in
the Ethernet frame.
Enable
alignment
EOP on FCS
word
Boolean • True
• False
True If turned on, the IP core aligns the
32-bit Frame Check Sequence (FCS)
error signal with the assertion of the
EOP by delaying the RX data bus to
match the latency of the FCS
computation. If turned off, the IP
core does not delay the RX data bus
to match the latency of the FCS
computation. If the parameter is
turned off, the FCS error signal, in
the case of an FCS error, is asserted
in a later clock cycle than the
relevant assertion of the EOP signal.
You must turn on this parameter if
your design relies on the
rx_inc_
octetsOK
signal..
2-8 IP Core Parameters
UG-01172
2015.05.04
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