Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 65)

Low Latency 40-100GbE IP Core RX Data Bus
The Low Latency 40-100GbE IP core RX datapath employs the Avalon-ST protocol. The Avalon-ST
protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data
stream (source) to a consumer of data (sink). The key properties of this interface include:
• Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
• A valid signal qualifies signals from source to sink.
Altera provides an Avalon-ST interface for both the LL 40GbE and LL 100GbE IP cores. In the 40GbE IP
core, the interface width is 256 bits, and in the 100GbE IP core, the interface width is 512 bits. In the LL
40GbE IP core, the client interface operates at a frequency of 312.5 MHz, and in the LL 100GbE IP core,
the client interface operates at a frequency of 390.625 MHz. The Avalon-ST interface requires that the
start of packet (SOP) always be in the MSB.
The RX MAC acts as a source and the client acts as a sink in the receive direction.
Figure 3-14: RX MAC to Client Interface
The Avalon-ST interface bus width varies with the IP core variation. In the figure, = 4 for the 40GbE
IP core and = 8 for the 100GbE IP core. is log
2
(8*).
l_rx_data[*64-1:0]
l_rx_empty[-1:0]
l_rx_startofpacket
l_rx_endofpacket
l_rx_error[5:0]
l_rx_valid
l_rx_fcs_valid
l_rx_fcs_error
l_rx_status[2:0]
RX
Client
RX
MAC
Table 3-5: Signals of the RX Client Interface
In the table, = 4 for the 40GbE IP core and = 8 for the 100GbE IP core. is log
2
(8*). The signals
are clocked by
clk_rxmac
.
Name Direction Description
l_rx_data[*64-1:0] Output RX data.
l_rx_empty[-1:0] Output Indicates the number of empty bytes on
l_rx_data
when
l_rx_endofpacket
is asserted, starting from the
least significant byte (LSB).
l_rx_startofpacket Output When asserted, indicates the start of a packet. The packet
starts on the MSB.
l_rx_endofpacket Output When asserted, indicates the end of packet.
3-20 Low Latency 40-100GbE IP Core RX Data Bus
UG-01172
2015.05.04
Altera Corporation Functional Description
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