Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 9)

Low Latency 40-100GbE IP Core Device Speed Grade Support
Table 1-3: Slowest Supported Device Speed Grades
Lists the slowest supported device speed grades for different variations of the Low Latency 40-100GbE IP core. IP
core variations that include a 1588 PTP module might require Quartus II seed sweeping to achieve a comfortable
timing margin.
MegaCore Function Device Family Supported Speed Grades
40GbE
Stratix V (GX) I3, C3
Stratix V (GT) I3, C2
Stratix V (GS) I3, C3
Arria 10 (GX, GT, GS) I2, C2
40GbE (40GBASE-KR4 option) Arria 10 (GX, GT, GS)
I2, C2
100GbE
Stratix V (GX) I2, C2
Stratix V (GT) I2, C2
Stratix V (GS) I2, C2
Arria 10 (GX, GT, GS) I2, C2
100GbE (CAUI–4 option) Arria 10 GT I2, C2
IP Core Verification
To ensure functional correctness of the Low Latency 40-100GbE IP core, Altera performs extensive
validation through both simulation and hardware testing. Before releasing a version of the Low Latency
40- and 100-Gbps Ethernet MAC and PHY IP core, Altera runs comprehensive regression tests in the
current or associated version of the Quartus ® II software.
Related Information
• Knowledge Base Errata for Low Latency 40-100GbE IP core
Exceptions to functional correctness are documented in the Low Latency 40-100GbE IP core errata.
• Altera IP Release Notes
Changes to the Low Latency 40-100GbE IP core are noted in the Altera IP Release Notes starting from
the Quartus II software v14.0 Arria 10 Edition.
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core Device Speed Grade Support 1-5
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function Altera Corporation
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