Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 97
322.265625 MHz ± 100 ppm. The ±100ppm value is required for any clock source providing the
transceiver reference clock.
Sync–E IP core variations are IP core variations for which you turn on Enable SyncE in the parameter
editor. These variations provide the RX recovered clock as a top-level output signal. This option is
available only for IP core variations that target an Arria 10 device.
The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommenda‐
tions, requires that the TX clock be filtered to maintain synchronization with the RX reference clock
through a sequence of nodes. The expected usage is that user logic drives the TX PLL reference clock with
a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain
synchronized.
Table 3-14: Clock Inputs
Describes the input clocks that you must provide.
Signal Name
Description
clk_status
Clocks the control and status interface. The clock quality and pin chosen
are not critical.
clk_status
is expected to be a 100–125 MHz clock.
In LL 40GBASE-KR4 variations, you must drive
clk_status
and
reconfig_status
from a single clock source.
reconfig_clk
Clocks the Arria 10 transceiver reconfiguration interface. The clock
quality and pin chosen are not critical.
reconfig_clk
is expected to be a
100 MHz clock; the allowed frequency range depends on Arria 10
transceiver requirements and is not IP core specific.
In LL 40GBASE-KR4 variations, you must drive
clk_status
and
reconfig_status
from a single clock source.
clk_ref
In IP core variations that target an Arria 10 device,
clk_ref
is the
reference clock for the transceiver RX CDR PLL. In other IP core
variations,
clk_ref
is the reference clock for the transceiver TX PLL and
the RX CDR PLL.
The frequency of this input clock must match the value you specify for
PHY reference frequency in the IP core parameter editor, with a
±100 ppm accuracy per the IEEE 802.3ba-2010 100G Ethernet Standard..
In addition,
clk_ref
must meet the jitter specification of the IEEE
802.3ba-2010 100G Ethernet Standard.
The PLL and clock generation logic use this reference clock to derive the
transceiver and PCS clocks. The input clock should be a high quality
signal on the appropriate dedicated clock pin.
clk_txmac_in
If you turn on Use external TX MAC PLL in the LL 40-100GbE
parameter editor, this clock drives the TX MAC. The port is expected to
receive the clock from the external TX MAC PLL and drives the internal
clock
clk_txmac
. The required TX MAC clock frequency is 312.5 MHz
for 40GbE variations, and 390.625 MHz for 100GbE variations. User logic
must drive
clk_txmac_in
from a PLL whose input is the PHY reference
clock,
clk_ref
.
3-52
Clocks
UG-01172
2015.05.04
Altera Corporation
Functional Description