Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 94)

The IP core includes the option to implement the following features:
• KR auto-negotiation provides a process to explore coordination with a link partner on a variety of
different common features. The 40GBASE-KR4 variations of the LL 40-100GbE IP core can auto-
negotiate only to a 40GBASE-KR4 configuration. Turn on the Enable KR4 Reconfiguration and
Enable Auto-Negotiation parameters to configure support for auto-negotiation.
• Link training provides a process for the IP core to train the link to the data frequency of incoming
data, while compensating for variations in process, voltage, and temperature. Turn on the Enable KR4
Reconfiguration and Enable Link Training parameters to configure support for link training.
• After the link is up and running, forward error correction (FEC) provides an error detection and
correction mechanism to enable noisy channels to achieve the Ethernet-mandated bit error rate (BER)
of 10 -12 . Turn on the Include FEC sublayer parameter to configure support for FEC.
The LL 40GBASE-KR4 IP core variations include separate link training and FEC modules for each of the
four Ethernet lanes, and a single auto-negotiation module. You specify the master lane for performing
auto-negotiation in the parameter editor, and the IP core also provides register support to modify the
selection dynamically.
Altera provides a testbench for LL 40GBASE-KR4 IP core variations with an Avalon-ST client interface
that generate their own TX MAC clock (Use external TX MAC PLL is turned off). Altera provides an
example project for all LL 40GBASE-KR4 IP core variations that generate their own TX MAC clock, to
assist you in integrating your LL 40GBASE-KR4 IP core into your complete design. You can examine the
testbench and example project for an example of how to drive and connect the 40GBASE-KR4 IP core.
IP core FEC functionality relies on register settings in the LL 40GBASE-KR4 registers and on some
specific register fields in the Arria 10 device registers.
To simulate correctly and to run correctly in hardware, you must drive the
reconfig_clk
and the
clk_status
inputs from the same source clock.
Related Information
Arria 10 Transceiver PHY User Guide
The 40GBASE-KR4 variations of the LL 40-100GbE IP core use the Altera Arria 10 10GBASE-KR PHY IP
core. Information about this PHY IP core, including functional descriptions of the listed features, is
available in the 10GBASE-KR PHY IP Core section of the Arria 10 Transceiver PHY User Guide. In this
section, functional descriptions of the AN and LT features are available in the "Auto Negotiation, IEEE
802.3 Clause 73" and "Link Training (LT), IEEE 802.3 Clause 72" sections.
Control and Status Interface
The control and status interface provides an Avalon-MM interface to the IP core control and status
registers. The Avalon-MM interface implements a standard memory-mapped protocol. You can connect
an embedded processor or JTAG Avalon master to this bus to access the control and status registers.
Table 3-12: Avalon-MM Control and Status Interface Signals
The
clk_status
clocks the signals on the LL 40-100GbE IP core control and status interface. The synchronous
reset_status
reset signal resets the interface.
Signal Name Direction Description
status_addr [15:0]
Input Address for reads and writes
status_read
Input Read command
UG-01172
2015.05.04
Control and Status Interface 3-49
Functional Description Altera Corporation
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