A. low latency 40-100gbe ip core example project, Low latency 40-100gbe ip core example project – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 154
Low Latency 40-100GbE IP Core Example
Project
A
2015.05.04
UG-01172
Altera provides an example Quartus II project with the Low Latency 40-100GbE IP core. This example
project can compile and configure on an Altera device. In addition, for Arria 10 IP core variations, you
can use this example project to view one option for connecting the external TX PLL or TX PLLs in your
design.
The example project is generated dynamically based on your parameter settings. For Stratix V variations,
the example project matches the parameter settings of your IP core variations. For Arria 10 variations, the
example project matches the parameter settings in the parameter editor at the time you click Example
Design. The example project is located in the
example_project/eth_ex_{40g,100g}_{sv,a10,kr4_a10}
directory.
Altera generates this example project for all non-CAUI-4 IP core variations with an Avalon-ST client
interface. Variations with External MAC PLL turned on will generate an example project that cannot
compile. The example projects do not exercise the Synchronous Ethernet feature.
You can compile the project and configure it on the Arria 10 FPGA Signal Integrity Development Kit or
the 100G Development Kit, Stratix V GX Edition. To use a different device or development kit, you must
modify the project as required for the different board and different device pinout (if relevant). A different
board might not support the clock frequencies the example project assumes.
The older, legacy Low Latency 40-100GbE IP core example projects are also generated when you generate
the example project just described. The older projects allow you to estimate static timing and resource
utilization. However, they use virtual pins and are provided only for compilation. The legacy example
projects are available for some IP core variations for which the device-configurable example project is not
available, notably, non-40GBASE-KR4 IP core variations with a custom client interface (without adapters)
and CAUI-4 IP core variations. The legacy example projects are available for the same IP core variations
for which testbenches are available. The legacy example project is located in
example_project/eth_{40g,
100g}_{s5,a10}
.
Related Information
•
Files Generated for Stratix V Variations
Illustrates the path to the example project's Quartus II project file in Stratix V variations. In Arria 10
variations, you are prompted to specify the location of the example project when you click Example
Design in the parameter editor.
•
Low Latency 40-100GbE IP Core Testbenches
Legacy example projects are available for the same IP core variations for which testbenches are
available.
•
Information about the correspondence between PLLs and transceiver channels in the Arria 10
transceivers, and information about how to configure an external PLL for your own design.
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