Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 172)

Word Addr Bit R/W Name Description
0x4D0
19:18 RW
Ctle depth
When using CTLE fine-grained tuning, determines
where to set final value in case of a tie. The
following values are defined:
• 00 = at lower tie
• 01 = 25% to upper tie
• 10 = 50% between lower and upper
• 11 = at upper tie
21:20 RW
rx_ctle_mode
default
= 00
Defines at what point to enable the RX CTLE in the
adaptation algorithm. The following values are
defined:
• 00 = never, the RX CTLE isn’t enabled or
adjusted.
• 01 = trigger CTLE before starting TX-EQ.
• 10 = trigger CTLE after finishing TX-EQ.
• 11 = trigger CTLE, both before starting, and
after finishing TX-EQ.
The default value is 001.
22 RW Reserved Reserved
28:24 RW Reserved Reserved
31:29 RW
max_post_step[2:0]
The number of EQ steps for the Post-Tap when in
max_mode
. You may receive
frame_lock_error
(reg 0xD2 bit-5) if you reduce Post-tap in min
when you have
ber_max
.
0x4D1
0 RW
Restart Link
training
When set to 1, resets the 10GBASE-KR start-up
protocol. When set to 0, continues normal
operation. This bit self clears. For more informa‐
tion, refer to the state variable mr_restart_training
as defined in Clause 72.6.10.3.1 and 10GBASE-KR
PMD control register bit (1.150.0) IEEE
802.3ap
-
2007.
4 RW
Updated TX Coef new
When set to 1, there are new link partner
coefficients available to send. The LT logic starts
sending the new values set in 0x4D4 bits[7:0] to the
remote device. When set to 0, continues normal
operation. This bit self clears. Must enable this
override in 0x4D0 bit16.
8 RW
Updated RX coef new
When set to 1, new local device coefficients are
available. The LT logic changes the local TX
equalizer coefficients as specified in 0x4D4
bits[23:16]. When set to 0, continues normal
operation. This bit self clears. Must enable the
override in 0x4D0 bit17.
UG-01172
2015.05.04
10GBASE-KR PHY Register Definitions B-13
Arria 10 10GBASE-KR Registers Altera Corporation
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