Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 40)

7. At marker 7, the 40GbE IP core asserts
l4_rx_valid
, indicating that it has valid data to send to the
client on
l4_rx_data[255:0]
.
8. At marker 8, the 40GbE IP core deasserts
l4_rx_valid
, indicating that the 40GbE IP core does not
have new valid data to send to the client on
l4_rx_data[255:0]
.
l4_rx_data[255:0]
remains
unchanged for a second cycle.
9. At marker 9, the IP core asserts
l4_rx_endofpacket
, indicating the end of the RX packet.
l4_rx_empty[4:0]
has a value of 0x1D, indicating that 29 least significant bytes of the last cycle of the
RX packet empty.
Note: The ready latency on the Avalon-ST TX client interface is 0.
Related Information
Avalon Interface Specifications
For more information about the Avalon-ST protocol.
Understanding the Testbench Behavior
The non-40GBASE-KR4 testbenches send traffic through the IP core in transmit-to-receive loopback
mode, exercising the transmit side and receive side of the IP core in the same data flow. These testbenches
send traffic to allow the Ethernet lanes to lock, and then send packets to the transmit client data interface
and check the data as it returns through the receive client data interface.
The 40GBASE-KR4 testbench sends traffic through the two IP cores in each direction, exercising the
receive and transmit sides of both IP cores. This testbench exercises auto-negotiation and link training,
and then sends and checks packets in data mode.
The Low Latency 40-100GbE IP core implements virtual lanes as defined in theIEEE 802.3ba-2010 40G
and 100G Ethernet Standard. The 40GbE IP cores are fixed at four virtual lanes and each lane is sent over
a 10 Gbps physical lane. The 100GbE IP cores are fixed at 20 virtual lanes; the 20 virtual lanes are typically
bit-interleaved over ten 10-Gbps physical lanes. When the lanes arrive at the receiver the lane streams are
in an undefined order. Each lane carries a periodic PCS-VLANE alignment tag to restore the original
ordering. The simulation establishes a random permutation of the physical lanes that is used for the
remainder of the simulation.
Within each virtual lane stream, the data is 64B/66B encoded. Each word has two framing bits which are
always either 01 or 10, never 00 or 11. The RX logic uses this pattern to lock onto the correct word
boundaries in each serial stream. The process is probabilistic due to false locks on the pseudo-random
scrambled stream. To reduce hardware costs, the receiver does not test alignments in parallel;
consequently, the process can be somewhat time-consuming in simulation.
In the 40GBASE-KR4 testbench, some register values are set to produce a shorter runtime. For example,
timeout counters and the number of steps used in link training are set to smaller values than would be
prudent in hardware. To override this behavior and use the normal settings in simulation, add the
following line to your IP core variation top-level file or to the testbench top-level file, alt_e40_avalon_kr4_
tb.sv :
`define ALTERA_RESERVED_XCVR_FULL_KR_TIMERS
Both the word lock and the alignment marker lock implement hysteresis as defined in the IEEE
802.3ba-2010 40G and 100G Ethernet Standard. Multiple successes are required to acquire lock and
multiple failures are required to lose lock. The “fully locked” messages in the simulation log indicate the
point at which a physical lane has successfully identified the word boundary and virtual lane assignment.
In the event of a catastrophic error, the RX PCS automatically attempts to reacquire alignment. The MAC
properly identifies errors in the datastream.
2-26 Understanding the Testbench Behavior
UG-01172
2015.05.04
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