Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 191
Date
Compatible ACDS
Version
Changes
• Clarified that IP core does not generate frames of eight bytes or less.
• Added waveform to illustrate register access on the control and
status interface, in the Control and Status Interface section
• Updated Differences Between Low Latency 40-100GbE IP Core and
40-100GbE IP Core v14.1 appendix with information about the
v14.1 IP core.
• Corrected misinformation about the IP core variations that support
the Enable TX CRC insertion parameter. Only IP core variations
that do not support flow control provide this parameter.
• Corrected order of
TX_PFC_DADDRH
(offset 0x60E) and
TX_PFC_
DADDRL
(offset 0x60D) registers.
• Corrected order of
TX_PFC_SADDRH
(offset 0x610) and
TX_PFC_
SADDRL
(offset 0x60F) registers.
• Corrected description of
RX_PAUSE_DADDR
registers at offsets 0x707
and 0x708. These registers are the same for standard flow control
and for priority-based flow control.
• Corrected installation directory figure for Stratix V variations, in
Installation and Licensing for LL 40-100GbE IP Core for Stratix V
Devices.
• Corrected erroneous indication that the value in
RETRANSMIT_
XOFF_HOLDOFF_EN
at offset 0x607 is indexed by the value in the
TX_
PAUSE_QNUMBER
register. In fact, the
RETRANSMIT_XOFF_HOLDOFF_
EN
register includes one bit for every flow-control priority queue
(one bit in case of standard flow control). Change is in Pause
Registers section.
• Fixed assorted typos and minor errors.
2014.08.18
14.0 and 14.0
Arria 10 Edition
• Updated for new Quartus II IP Catalog, which replaces the
MegaWizard Plug-In Manager starting in the Quartus II sofware
v14.0. Changes are located primarily in Getting Started chapter.
Reordered the chapter to accommodate the new descriptions.
• Updated the Installation section to clarify that the LL 40-100GbE IP
core v14.0 is available from the Self-Service Licensing Center, and
the LL 40-100GbE IP core v14.0 Arria 10 Edition is included in the
Quartus II software installation.
• Added new, additional allowed value for PHY reference clock
frequency: 322.265625 MHz.
• Added new parameter option to configure an inter-packet gap of 8.
• Added new parameter option to configure the IP core without
adapters, exposing a custom streaming client interface that is
narrower than the Avalon-ST interface. This option is available in
IP cores configured without a 1588 PTP module and without an
internal flow control scheme. You must select the custom streaming
client interface or the Avalon-ST client interface. Your selection
applies to both the RX and TX client interfaces.
UG-01172
2015.05.04
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
D-5
Additional Information
Altera Corporation