Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 115)

Addr Name Bit Description HW Reset
Value
Access
0x340
PHY_REFCLK_
KHZ
[31:0] Reference clock frequency in KHz, assuming
the
clk_status
clock has the frequency of
100 MHz. The reference clock frequency is
the value in the
PHY_REFCLK_KHZ
register
times the frequency of the
clk_status
clock,
divided by 100.
RO
0x341
PHY_RXCLK_
KHZ
[31:0] RX clock (
clk_rxmac
) frequency in KHz,
assuming the
clk_status
clock has the
frequency of 100 MHz. The RX clock
frequency is the value in the
PHY_REFCLK_KHZ
register times the frequency of the
clk_
status
clock, divided by 100.
RO
0x342
PHY_TXCLK_
KHZ
[31:0] TX clock (
clk_txmac
) frequency in KHz,
assuming the
clk_status
clock has the
frequency of 100 MHz. The TX clock
frequency is the value in the
PHY_REFCLK_KHZ
register times the frequency of the
clk_
status
clock, divided by 100.
RO
0x343
PHY_RECCLK_
KHZ
[31:0] RX recovered clock frequency in KHz,
assuming the
clk_status
clock has the
frequency of 100 MHz. The RX recovered
clock frequency is the value in the
PHY_
REFCLK_KHZ
register times the frequency of
the
clk_status
clock, divided by 100.
RO
0x344
PHY_
TXIOCLK_KHZ
[31:0] TX PMA clock frequency in KHz, assuming
the
clk_status
clock has the frequency of
100 MHz. The TX PMA clock frequency is
the value in the
PHY_REFCLK_KHZ
register
times the frequency of the
clk_status
clock,
divided by 100.
RO
Link Fault Signaling Registers
Table 3-21: LINK_FAULT_CONFIG Register—Offset 0x405
Name Bit Description
Reset
Value
Access
Unidir Enable [1]
When asserted, the IP core includes Clause 66 support for
remote link fault reporting on the Ethernet link.
1'b0
RW
Link Fault
Reporting
Enable
[0]
When asserted, the PCS generates remote fault sequence
on the Ethernet link, if conditions are met.
1’b1 RW
3-70 Link Fault Signaling Registers
UG-01172
2015.05.04
Altera Corporation Functional Description
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