Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 34)

Note: If your Arria 10 design includes multiple instances of the LL 40-100GbE IP core, do not use the
ATX PLL HDL code provided with the IP core. Instead, generate new TX PLL IP cores to connect
in your design.
The number of external PLLs you must generate or instantiate depends on the distribution of your
Ethernet TX serial lines across physical transceiver channels and banks. You specify the clock network to
which each PLL output connects by setting the clock network in the PLL parameter editor. The example
project demonstrates one possible choice, which is compatible with the ATX PLL provided with the LL
40-100GbE IP core.
You must connect the
tx_serial_clk
input pin for each Low Latency 40-100GbE IP core PHY link to
the output port of the same name in the corresponding external PLL. You must connect the
pll_locked
input pin of the Low Latency 40-100GbE IP core to the logical AND of the
pll_locked
output signals of
the external PLLs for all of the PHY links.
User logic must provide the AND function and connections. Refer to the example project for example
working user logic including one correct method to instantiate and connect an external PLL.
Related Information
• External Transceiver PLL on page 3-27
• Low Latency 40-100GbE IP Core Example Project on page 5-1
The Arria 10 example project provides an example of how to connect external PLLs to your Arria 10
Low Latency 40-100GbE IP core.
• Pin Assignments on page 2-18
• Arria 10 Transceiver PHY User Guide
Information about the correspondence between PLLs and transceiver channels, and information about
how to configure an external transceiver PLL for your own design. You specify the clock network to
which the PLL output connects by setting the clock network in the PLL parameter editor.
External Time-of-Day Module for Variations with 1588 PTP Feature
Low Latency 40-100GbE IP cores that include the 1588 PTP module require an external time-of-day
(TOD) module to provide a continuous flow of current time-of-day information. The TOD module must
update the time-of-day output value on every clock cycle, and must provide the TOD value in the V2
format.
The example project you can generate for your IP core PTP variation includes a TOD module,
implemented as two distinct, simple TOD modules, one connected to the TX MAC and one connected to
the RX MAC.
Table 2-7: TOD Module Required Connections
Required connections for TOD module, listed using signal names for TOD module that is included with the
example project. If you create your own TOD module it could have different signal names. For example, a TOD
module might have a single TOD_out signal. However, these connections illustrate the IP core's requirements.
TOD Module Signal LL 40-100GbE IP Core Signal
rst_txmac
(input) Drive this signal from the same source as the
reset_async
input signal to the LL 40-100GbE IP core.
rst_rxmac
(input) Drive this signal from the same source as the
reset_async
input signal to the LL 40-100GbE IP core.
tod_txmclk[95:0]
(output)
tod_txmac_in[95:0]
(input)
2-20 External Time-of-Day Module for Variations with 1588 PTP Feature
UG-01172
2015.05.04
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