Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 193
Date
Compatible ACDS
Version
Changes
• Corrected addresses of the following statistics registers:
•
CNTR_TX_CRCERR
registers from 0x804-0x805 to 0x806-0x807.
•
CNTR_TX_FCS
registers from 0x806-0x807 to 0x804-0x805
•
CNTR_RX_CRCERR
registers from 0x904-0x8905 to 0x906-0x907.
•
CNTR_RX_FCS
registers from 0x906-0x907 to 0x904-0x905
• Corrected direction of
clk_txmac
and
clk_rxmac
in table in Signals
section to Output.
• Added HW reset values for PHY registers that have them. All PHY
register listings except those for the identifier string registers and
the frequency registers now list a HW reset value.
• Added basic information to description of HI BER field of
PHY_
RXPCS_STATUS
register.
2014.04.28
13.1 Update 3
13.1 Arria 10
Edition Update 2
• Corrected presentation of resource utilization numbers for Stratix V
device family to clarify size of IP core without 1588 PTP module
• Renamed Pause Registers tables to Ethernet Flow Control (Pause
Functionality) Registers for consistency
• In Low Latency 40-100GbE IP Core Address Map table, clarified
that the 1588 PTP registers are only available if you turn on the
parameter to include the 1588 PTP module in your IP core instance.
The same information was already available in the table for other
registers that are only available if you turn on the associated
parameter.
• Fixed assorted typos (column width in TX MAC Configuration
Registers table, reset value widths of
RX_PAUSE_DADDR0
register in
RX Ethernet Flow Control Registers table and of
TX_PTP_CLOCK_
PERIOD
register in TX 1588 PTP Registers table)
2014.04.11
13.1 Update 3
13.1 Arria 10
Edition Update 2
• Added resource utilization numbers for Stratix V device family.
• Corrected supported Stratix V device speed grade information for
Low Latency 100GbE IP cores.
• Added note to supported Stratix V device speed grade information
table clarifying that Quartus II seed sweeping might be required for
variations that include a 1588 PTP module to achieve a comfortable
timing margin.
UG-01172
2015.05.04
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
D-7
Additional Information
Altera Corporation