How to contact altera – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 194
Date
Compatible ACDS
Version
Changes
2014.03.06
13.1 Update 3
13.1 Arria 10
Edition Update 2
• Corrected descriptions of pause enable registers:
• Added description for
TX_XOF_EN
register at offset 0x60A.
• Enhanced description of
cfg_enable
field of
RX_PAUSE_ENABLE
register at offset 0x705 to clarify the different functions of the
TX_XOF_EN
and
RX_PAUSE_ENABLE
registers in enabling the IP
core to incoming pause frames.
• Enhanced description of the
TX_PAUSE_EN
register at offset
0x605 to clarify the different functions of the
TX_XOF_EN
and
TX_
PAUSE_EN
registers.
• In "Differences Between Low Latency 40-100GbE IP Core and 40-
100GbE IP Core v13.1", enhanced the description of the differences
in pause frame control and processing and in use of maximum
frame size register information.
• Updated "Congestion and Flow Control Using Pause Frames" with
the enable register field information.
• Updated "Pause Control Frame Filtering" with the new enable
register field information and to clarify that by default, RX pause
frame processing is enabled.
• Enhanced "Low Latency 40-100GbE Example Project" to clarify that
some project aspects are relevant only for Arria 10 devices.
• Corrected "Clocks" section to include
tx_serial_clk
input clocks
and to list
clk_rxmac
and
clk_txmac
as output clocks.
2014.02.17
13.1 Update 3
13.1 Arria 10
Edition Update 2
Initial release.
How to Contact Altera
Table D-2: How to Contact Altera
To locate the most up-to-date information about Altera products, refer to this table. You can also contact your
local Altera sales office or sales representative.
Contact
Contact Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Product literature
Website
www.altera.com/literature
Nontechnical support: general
D-8
How to Contact Altera
UG-01172
2015.05.04
Altera Corporation
Additional Information