Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 95)

Signal Name Direction Description
status_write
Input Write command
status_writedata [31:0]
Input Data to be written
status_readdata [31:0]
Output Read data
status_readdata_valid
Output Read data is ready for use
status_waitrequest
Output Busy signal indicating control and status interface cannot
currently respond to requests
status_read_timeout
Output Timeout signal indicating read data did not arrive when
expected. Hardwired timeout counter is set so that this
timeout should only occur in the presence of an error
condition, such as
status_addr
with an undefined value.
This signal is not an Avalon-MM defined signal
The status interface is designed to operate at a low frequencies, typically 100 MHz, so that control and
status logic does not compete for resources with the surrounding high speed datapath.
Figure 3-26: Read and Write Register Access Example
The waveform demonstrates a write-read-write sequence of back-to-back register accesses. The delay
from the time the application asserts
status_read
until the IP core asserts
status_readdata_valid
and
deasserts
status_waitrequest
is approximately 80
clk_status
cycles in this example.
clk_status
reset_status
status_write
status_read
status_addr[15:0]
status_writedata[31:0]
status_readdata[31:0]
status_readdata_valid
status_waitrequest
0407
0000_2580
xxx_xx00 xxxx_0000 xx00_0000
42 Clock Cycles
Related Information
• Software Interface: Registers on page 3-64
• Low Latency 40-100GbE IP Core Registers on page 3-67
• Avalon Interface Specifications
For more information about the Avalon-MM protocol, including timing diagrams, refer to the Avalon
Memory-Mapped Interfaces chapter.
3-50 Control and Status Interface
UG-01172
2015.05.04
Altera Corporation Functional Description
Send Feedback