Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 126
Address
Name
Bit
Description
HW
Reset
Value
Access
LT VODMin
ovrd, Lane 0
[12:8] Override value for the VODMINRULE
parameter on Lane 0. When enabled, this value
substitutes for the VMINRULE to allow
channel-by-channel override of the device
settings. This override only effects the local
device TX output for this channel.
The value to be substituted must be less than the
INITMAINVAL parameter and greater than the
VMINRULE parameter for proper operation.
0x19
(25
decim
al) for
simula
ton; 0
for
compil
ation
RW
LT VODMin
ovrd Enable,
Lane 0
[13]
When set to 1, enables the override value for the
VODMINRULE parameter stored in the
LT
VODMin ovrd, Lane 0
register field.
1 for
simula
tion; 0
for
compil
ation
RW
LT VPOST
ovrd, Lane 0
[21:16
]
Override value for the VPOSTRULE parameter
on Lane 0. When enabled, this value substitutes
for the VPOSTRULE to allow channel-by-
channel override of the device settings. This
override only effects the local device TX output
for this channel.
The value to be substituted must be greater than
the INITPOSTVAL parameter for proper
operation.
6 for
simula
tion; 0
for
compil
ation
RW
LT VPOST
ovrd Enable,
Lane 0
[22]
When set to 1, enables the override value for the
VPOSTRULE parameter stored in the
LT VPOST
ovrd, Lane 0
register field.
1 for
simula
tion; 0
for
compil
ation
RW
LT VPre
ovrd, Lane 0
[28:24
]
Override value for the VPRERULE parameter on
Lane 0. When enabled, this value substitutes for
the VPOSTRULE to allow channel-by-channel
override of the device settings. This override only
effects the local device TX output for this
channel.
The value to be substituted must be greater than
the INITPREVAL parameter for proper
operation.
4 for
simula
tion; 0
for
compil
ation
RW
UG-01172
2015.05.04
LL 40GBASE-KR4 Registers
3-81
Functional Description
Altera Corporation