Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 178)

Word Addr Bit R/W Name Description
0x4D4
29:24 RO
LP coefficient
status[5:0]
Status report register reflects the contents of the
second, 16-bit word of the training frame most
recently received from the control channel: The
following fields are defined:
• [5:4]: Coefficient (+1)
• 2'b11: Maximum
• 2'b01: Minimum
• 2'b10: Updated
• 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• n [1:0]: Coefficient (-1) (same encoding as
[5:4])
For more information, refer to 10G BASE-KR LP
status report register bits (1.153.5:0) in Clause
45.2.1.79 of IEEE 802.3ap-2007.
30 RO
LP Receiver ready
When set to 1, the link partner receiver has
determined that training is complete and is
prepared to receive data. When set to 0, the link
partner receiver is requesting that training
continue.
Values for the receiver ready bit are defined in
Clause 72.6.10.2.4.4. For more information, refer to
10G BASE-KR LP status report register bits
(1.153.15) in Clause 45.2.1.79 of IEEE 802.3ap-
2007.
0x4D5
4:0 R
LT V
OD
setting
Stores the most recent TX V
OD
setting trained by
the link partner's RX based on the LT coefficient
update logic driven by Clause 72. It reflects Link
Partner commands to fine-tune the TX
preemphasis taps.
13:8 R
LT Post-tap setting
Stores the most recent TX post-tap setting trained
by the link partner’s RX based on the LT coefficient
update logic driven by Clause 72. It reflects Link
Partner commands to fine-tune the TX
pre-emphasis taps.
20:16 R
LT Pre-tap setting
Store the most recent TX pre-tap setting trained by
the link partner’s RX based on the LT coefficient
update logic driven by Clause 72. It reflects Link
Partner commands to fine-tune the TX
pre-emphasis taps.
UG-01172
2015.05.04
10GBASE-KR PHY Register Definitions B-19
Arria 10 10GBASE-KR Registers Altera Corporation
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