Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 192
Date
Compatible ACDS
Version
Changes
• Added new parameter option to configure priority-based flow
control. This option is available in 100GbE variations with Tx CRC
insertion turned on and with an Avalon-ST client interface.
• Adds a new parameter to specify between 1 and 8 priority
queues, inclusive.
• Expands the width of the pause signals to the number of priority
queues. Each bit refers to the corresponding priority queue.
• Modifies the pause registers to apply to both standard and
priority-based flow control. In some cases the register fields do
not change and in others the register field widens to one bit per
priority queue. In the case of three registers, modifies them
drastically so they are essentially different registers in the case of
priority-based flow control:
•
TX_XOF_EN
at offset 0x60A has no equivalent register in
priority-based flow control. The replacement register at this
offset,
TX_PAUSE_QNUMBER
, holds the queue number of the
queue to which the current contents of the
RETRANSMIT_
XOFF_HOLDOFF_EN
,
RETRANSMIT_XOFF_HOLDOFF_QUANTA
, and
TX_PAUSE_QUANTA
apply.
•
RX_PAUSE_DADDR1
and
RX_PAUSE_DADDR0
are replaced with
RX_PFC_DADDRH
and
RX_PFC_DADDRL
, which divide the 48-bit
destination address for matching differently than the
standard flow-control registers.
• Adds new pause registers
CFG_RETRANSMIT_EN
,
CFG_
RETRANSMIT_QUANTA
,
TX_PFC_DADDRH
,
TX_PFC_DADDRL
,
TX_PFC_
SADDRH
, and
TX_PFC_SADDRL
.
• Stratix V variations no longer support an internal transceiver
reconfiguration controller. User logic must instantiate a transceiver
reconfiguration controller.
• Removed registers at offsets 0x350, 0x351, 0x352, and 0x353.
• Added signals
reconfig_from_xcvr
,
reconfig_to_xcvr
, and
reconfig_busy
in Stratix V variations.
• Updated Differences Between Low Latency 40-100GbE IP Core and
40-100GbE IP Core v14.1 appendix with new Low Latency 40-
100GbE IP core features.
• Updated description of example project to clarify the Arria 10
project no longer implements additional input clocks to
demonstrate static timing derivation.
• Added instructions to generate the testbench and example project
in the 14.0 and 14.0 Arria 10 Edition versions of the IP core.
• Reorganized the testbench sections of Chapter 2, Getting Started.
D-6
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
UG-01172
2015.05.04
Altera Corporation
Additional Information