Figure 5–13 – Altera IP Compiler for PCI Express User Manual

Page 99

Chapter 5: IP Core Interfaces

5–13

Avalon-ST Interface

August 2014

Altera Corporation

IP Compiler for PCI Express User Guide

Figure 5–12

shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs

for a four dword header with non-qword aligned addresses. In this example,
rx_st_empty

is low because the data ends in the upper 64 bits of rx_st_data.

Figure 5–13

shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs

for a four dword header with qword aligned addresses.

For a complete description of the TLP packet header formats, refer to

Appendix A,

Transaction Layer Packet (TLP) Header Formats

Figure 5–12. 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-DWord Header TLPs with non-QWord Aligned Addresses

clk

rx_st_valid

rx_st_data[127:96]

rx_st_data[95:64]

rx_st_data[63:32]

rx_st_data[31:0]

rx_st_sop

rx_st_eop

rx_st_empty

Header 3

Data 2

Header 2

Data 1

Data n

Header 1

Data 0

Data n-1

Header 0

Data n-2

Figure 5–13. 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-DWord Header TLPs with QWord Aligned Addresses

clk