Altera IP Compiler for PCI Express - Manual (Page 105)

Chapter 5: IP Core Interfaces 5–19
Avalon-ST Interface
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Figure 5–18 illustrates the mapping between Avalon-ST TX packets and PCI Express
TLPs for a four dword header with qword aligned addresses with a 64-bit bus.
Figure 5–19 illustrates the mapping between Avalon-ST TX packets and PCI Express
TLPs for four dword header with non-qword aligned addresses with a 64-bit bus.
Figure 5–20 shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
for a three dword header with qword aligned addresses.
Figure 5–18. 64-Bit Avalon-ST tx_st_data Cycle Definition for 4–DWord TLP with QWord Aligned Address
Notes to Figure 5–18 :
(1) Header0 = {pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3}
(2) Header1 = {pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7}
(3) Header2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11}
(4) Header3 = pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15}, 4 dword header only
(5) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}
(6) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}
clk
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
Header1 Header3 Data1
Header0 Header2 Data0
1 2 3
Figure 5–19. 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-DWord Header with Non-QWord Aligned Address
clk
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
Header 1 Header3 Data0 Data2
Header 0 Header2 Data1
Figure 5–20. 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-DWord Header TLP with QWord Aligned Address
Data3
Header2 Data 2
Header1 Data1 Data(n)
Header0 Data0 Data(n-1)
clk
tx_st_valid
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
tx_st_empty