Altera IP Compiler for PCI Express - Manual (Page 222)

14–2 Chapter 14: External PHYs
External PHY Support
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
1 The refclk is the same as pclk, the parallel clock provided by the external PHY. This
document uses the terms refclk and pclk interchangeably.
■ clk125_out is a 125 MHz output that has the same phase-offset as refclk. The
clk125_out must drive the clk125_in input in the user logic as shown in the
Figure 14–1 . The clk125_in is used to capture the incoming receive data and also
is used to drive the clk125_in input of the IP core.
■ clk125_early is a 125 MHz output that is phase shifted. This phase-shifted output
clocks the output registers of the transmit data. Based on your board delays, you
may need to adjust the phase-shift of this output. To alter the phase shift, copy the
PLL source file referenced in your variation file from the
<path>/ip/ip_compiler_for_pci_express/lib directory, where is the
directory in which you installed the IP Compiler for PCI Express, to your project
directory. Then use the parameter editor to edit the PLL source file to set the
required phase shift. Then add the modified PLL source file to your Quartus II
project.
■ tlp_clk62p5 is a 62.5 MHz output that drives the tlp_clk input of the IP core
when the IP Compiler for PCI Express internal clock frequency is 62.5 MHz.
16-bit SDR Mode with a Source Synchronous TXClk
The implementation of the 16-bit SDR mode with a source synchronous TXClk is
shown in
Figure 14–2 and is included in the file <variation name>.v or <variation
name>.vhd. In this mode the following clocking scheme is used:
■ refclk is used as the clk125_in for the core
Figure 14–1. 16-bit SDR Mode - 125 MHz without Transmit Clock
IP Compiler
for PCI Express
clk125_in
tlp_clk
refclk clk125_out
ENB
A
D
Q 1
Q 4
ENB
Q
Q
A 1
D 4
Mode 1
PLL
clk125_early tlp_clk_62p5
refclk (pclk)
rxdata
txdata
clk125_out
External connection
in user logic
ENB
A
D
Q 1
Q 4
clk125_in